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    DPDK MASTERY · FULL ROADMAP · 3 PHASES

    ⚡ DPDK Learning Roadmap

    3–4 months · Intel / Mellanox NICs · C · 6 modules · 7 mini-projects · Production SASE-DP context

    3Phases
    6Modules
    7Projects
    14+Weeks
    SASECapstone

    PHASE TIMELINE

    1
    Foundation & Memory
    Weeks 1–5
    Why the Linux kernel packet path fails at 100G — interrupts, sk_buff, memory copies, context switches. DPDK's answer: Poll Mode Drivers, hugepages, zero-copy, user-space NIC ownership. Full DPDK software stack from PMD → ethdev → rte_mempool → rte_mbuf → EAL. PCIe device binding with VFIO and IOMMU. Hugepage anatomy, IOVA, DMA mapping. rte_mempool pre-allocation mechanics (per-lcore cache, bulk get/put). rte_mbuf layout: buf_addr, data_off, pkt_len, ol_flags, headroom, chained mbufs.
    🔧 Foundation & EAL 💾 Hugepages, mempool & mbuf
    kernel path overheads PMD polling rte_eal_init() VFIO-PCI IOMMU hugepages IOVA rte_mempool rte_mbuf zero-copy
    📦 Project 1: DPDK Hello World + EAL Probe 📦 Project 2: mbuf Inspector — Decode Every Field
    2
    Core Mechanics
    Weeks 6–10
    Two modules covering DPDK's complete runtime machinery. PMD & Port Config: NIC descriptor rings, DD bit handshake, rx_burst / tx_burst hot path, full port configuration sequence (dev_configure → queue_setup → dev_start), offloads, stats. RSS: Toeplitz hash in hardware, RETA table, symmetric RSS key, power-of-2 worker count requirement. rte_ring: lock-free SPSC/MPMC circular buffer, CAS mechanics, bulk enqueue/dequeue. rte_distributor: fan-out from one RX core to N workers, work tagging, flow affinity. Application Models: run-to-completion vs pipeline, when to use each.
    🔌 PMD & Port Config 🔄 rte_ring, Distributor & App Models
    rte_eth_rx_burst DD bit descriptor rings RSS Toeplitz RETA symmetric RSS rte_ring CAS MPMC rte_distributor pipeline model
    📦 Project 3: L2 Forwarder with RSS Verification 📦 Project 4: Ring-Based Worker Pipeline
    ⚠️ Phase 1 memory knowledge is prerequisite — PMD and ring patterns build directly on mempool and mbuf internals.
    3
    Advanced Topics & Production
    Weeks 11–14+
    Production-grade DPDK design and operations. Multi-Process: primary/secondary model, shared mempools and rings, named object lookup, hot-restart secondaries — exactly the pattern used in Jio SASE-DP. rte_flow: hardware flow classification and queue steering with zero CPU cost, match / action model, flow priority and groups. NUMA: socket-aware allocation, lcore binding, cache-line alignment, false sharing. Packet Processing Patterns: prefetching, batching, branch elimination. Performance Tuning: CPU isolation, hugepage sizing, burst tuning, PMD stats, benchmarking. Debugging: mbuf leaks, imissed counter, mempool exhaustion, common pitfalls.
    🌐 Multi-Process, rte_flow & NUMA 📈 Patterns, Tuning & Debugging
    primary/secondary rte_mempool_lookup rte_flow_create FDIR NUMA-aware alloc cache-line align prefetch isolcpus imissed mbuf leak
    📦 Project 5: Multi-Process SASE-DP Skeleton 📦 Project 6: rte_flow Hardware Classifier 📦 Project 7: End-to-End URL Filter Dataplane

    ALL MINI-PROJECTS

    # Project Phase Key Skills
    1 DPDK Hello World + EAL Probe P1 rte_eal_init, lcore enumeration, hugepage check
    2 mbuf Inspector — Decode Every Field P1 rte_mbuf layout, ol_flags, pkt_len, headroom
    3 L2 Forwarder with RSS Verification P2 rx_burst, tx_burst, MAC swap, RSS queue affinity
    4 Ring-Based Worker Pipeline P2 rte_ring SPSC, producer/consumer cores, backpressure
    5 Multi-Process SASE-DP Skeleton P3 primary/secondary, named pool lookup, hot-restart
    6 rte_flow Hardware Classifier P3 rte_flow_create, 5-tuple matching, queue steering
    7 End-to-End URL Filter Dataplane P3 Full pipeline: RX → classify → filter → TX → stats
    ← DPDK Hub Start: Phase 1 →