ASSETI/O · pcie
PCI Express
The point-to-point interconnect that joins add-in cards — network cards, GPUs, NVMe drives — to the CPU.
On the system board, PCIe is a slot and the wiring behind it: lanes that run from the slot's contacts to the
root complex inside the CPU. This model is that board side. The other half, the card's edge connector, belongs to
each card — the AxioByte NIC's x8 connector matches these contacts exactly.
Parts
- the x8 socket: 98 contacts and the key
- contacts 1–11: power, reset, clock
-
lanes: two differential pairs each
- the eight lanes as one x8 link (logical)
Lanes and the link
A lane is two differential pairs, one for each direction, so data flows both ways at once. A link bundles lanes —
x1, x4, x8, x16 — and stripes data across them byte by byte. This slot is x8: about 7.9 GB/s each way at PCIe 3.0,
15.8 GB/s at PCIe 4.0. When a card comes up, both ends train the link to the widest width and fastest rate they
share.
Endpoint and root complex
Every link has exactly two ends. Upstream is the root complex, built into the CPU, which turns PCIe transactions
into memory accesses. Downstream is the endpoint — the card in the slot. A card reaches memory by sending
memory-read and memory-write transactions up the link: that is how a NIC's DMA engine places packets in host RAM
without the CPU copying them. Where more devices are needed than the CPU has root ports, a PCIe switch fans one
link out into several.
Where AxioByte uses it
The NIC plugs into a slot like this one. PCIe is the link in the
NIC to host memory system: the NIC seated in this slot, the eight lanes
running as one x8 link to the CPU's root complex, and the DMA path from the NIC
through PCIe into host memory.
Asset
- Id
- pcie · version 1.0.0
- Status
- released in experiences v1.2.0 · hero
- Concept
- pcie (I/O)
- Renderers
- Three.js (live), Manim actor (flat)
- Ports
- endpoint — the slot opening; root_complex — the lanes' vias, toward the CPU