AxioByte · Networking

NIC to host memory

A system: card, link, CPU, memory

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COMPOSITIONnic_host

NIC to host memory

How a received packet gets from a network card into the computer's memory: the card, the PCIe link, the CPU and host memory, connected as one system.

This is a composition: four assets from the AxioByte library, each the same model as on its own page, placed and connected. Nothing here is a new piece of hardware. The board they would all sit on is not modelled — the links between the assets are drawn schematically, not as copper.

The assets

the card, in its slot — its page
the slot and its eight lanes — its page
root complex and memory controller — its page
the modules and their allocations — its page

How they connect

the NIC's edge connector seated in the PCIe slot
the eight lanes, from the slot to the CPU's root complex
from the CPU's memory controller to both modules

The card touches the slot; the other two are links across a motherboard that is not drawn. The eight lanes arrive at the CPU as one x8 link, and the memory channels leave it as one connection that reaches both modules.

DMA

Before any packet arrives, the driver has allocated packet buffers in host memory and written their addresses into a descriptor ring, also in host memory. When a packet arrives, the NIC's DMA engine reads a descriptor, then sends the packet up the PCIe link as memory writes. The CPU's root complex hands them to its memory controller, which writes them into the buffer the descriptor named. No core copies the bytes; software finds the packet where it landed.

Composition

Id: nic_host
Instances: nic · pcie · cpu · host_memory, each at scale 1
Connections: card ↔ slot (mate); PCIe x8 and memory channels (routes)
Interaction: dma — from the NIC to the packet-buffer region
Contract: assets/compositions/nic_host.yaml

What is simplified

The assets sit closer together than on a real motherboard, and the links between them are schematic. One slot, one CPU, two modules; real systems have more of each. The DMA path is drawn as one flow of packets; in reality the NIC also reads descriptors and writes status back, and memory writes are interleaved across channels.

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