ASSET Memory · host_memory
Host memory
The computer's main memory — the DRAM the CPU's memory controller serves. Cores reach it through their caches;
devices such as a NIC reach it directly, by DMA.
This page shows host memory on its own, in two layers kept apart on purpose. At the back, the physical memory:
modules of DRAM chips. In front, a logical map of the address space those modules provide, and what software has
allocated in it. The map is a diagram, not hardware, and it is not to scale.
Physical memory
Module 0 a DIMM: DRAM chips on a small boardModule 1 a second module — memory is added in modules
Allocation
Software sees memory as one range of physical addresses, handed out in pages by the operating system. Rings and
buffers are not special hardware: they are allocations, in ordinary DRAM, among everything else memory holds.
Address space all of memory, addressed from 0 upDescriptor region a ring of buffer addresses for the NICPacket buffers where the NIC writes packetsOther memory kernel, applications, free pages
Descriptor rings and packet buffers
To receive, a driver allocates packet buffers and a descriptor ring, and writes a buffer's address into each
descriptor. The NIC reads the descriptors, writes each packet it receives into the buffer a descriptor names, and
marks the descriptor done; software finds the packet where it landed. A descriptor holds addresses and status —
never the packet bytes. That is why a NIC and a data plane such as DPDK live and die by host memory: every packet
arrives there.
Where it sits
Host memory hangs off the CPU . The CPU's memory controller drives the memory
channels; each channel runs across the motherboard to DIMM slots. The modules' edge contacts are this asset's
memory_interface, the counterpart of the CPU's own memory_interface. The CPU is not in
this scene: this page shows the memory on its own.
PCIe and DMA
A NIC reaches host memory through PCIe : its reads
of descriptors and its writes of packets travel up the link to the CPU's root complex, which passes them to memory —
no core copies the bytes. That transfer is DMA, an interaction between the card and memory. It is not a part of
this asset, and this page does not draw it; the NIC to host memory system
does — NIC → PCIe → CPU → host memory, with this asset as the memory the packets land in.
Asset
Id host_memory · version 1.0.0
Status released in experiences v1.2.0 · hero
Concept host_memory (memory)
Renderers Three.js (live), Manim actor (flat)
Ports memory_interface — the modules' edge contacts, toward the CPU
What is simplified
Two generic modules; real systems have one or more per memory channel, and their count, size and generation vary.
The map shows what memory holds, not where bytes sit: the memory controller interleaves addresses across channels
and modules, so a region that looks contiguous here is spread across both. Real rings hold hundreds of descriptors
and real systems thousands of buffers, in pages scattered through memory; the regions are drawn large enough to
read. DRAM internals — banks, rows, refresh — and memory-mapped device addresses are left out.