ASSETComputing · cpu
The CPU
The processor that runs a computer's software: a set of cores that execute instructions, with caches, a memory
controller and PCIe root ports on the same chip.
This model is a generic desktop processor package, not any vendor's part. The package is physical; the regions
drawn on the die when you look inside are an educational layout — no real CPU is laid out exactly like this.
Physical structure
- the metal lid the cooler presses on
- the silicon, bonded face down
- fans the die's bumps out to the lands
- where every connection is made
Inside the CPU
- execute instructions
- keeps recent memory on the die
- talks to DRAM
- the CPU's end of every PCIe link
A core
A core is a complete processor: it fetches, decodes and executes one stream of instructions (two, with
simultaneous multithreading), with its own private L1 and usually L2 caches. Several cores run several streams
truly at once. In a DPDK data plane a core is often dedicated to one job — polling one NIC queue.
Cache
Caches keep recently used memory close to the cores, in fixed-size cache lines — typically 64 bytes. A core looks
in its own L1 and L2, then the cache all cores share, and only then goes out to DRAM, far slower.
Memory interface
The memory controller turns cache misses into DRAM reads and writes over the memory channels. Those channels leave
the package through their own group of lands — this asset's memory_interface — and run to the DIMM
slots of host memory.
PCIe and I/O
The root complex is the CPU's end of every PCIe link. Its lanes leave through another
group of lands — the pcie_root_complex interface — and run across the motherboard to the slots. The
NIC to host memory system shows that chain: NIC
→ PCIe → CPU → host memory, the eight lanes arriving as one x8 link. When the NIC writes a packet into memory by DMA,
the write comes up the link to the root complex, which passes it on to the memory controller — the cores do not copy
it.
Asset
- Id
- cpu · version 1.0.0
- Status
- released in experiences v1.2.0 · hero
- Concept
- cpu (compute)
- Renderers
- Three.js (live), Manim actor (flat, iso)
- Ports
- pcie_root_complex — the PCIe lands, to the PCIe asset; memory_interface — the memory lands, to host memory
Technical notes and limitations
One generic package with one die. Core count, cache size, the region layout and the land fields are illustrative;
the model makes no claim about any real processor's floorplan, pinout or specifications. The socket belongs to the
motherboard and is not part of this asset.